1. Field of the Invention
The present invention relates to a multi-gate MOS transistor and a method of manufacturing the same and, more particularly, to a multi-gate MOS transistor having two silicon fins which are perpendicularly stacked and using four side surfaces of an upper silicon fin and three side surfaces of a lower silicon fin as a channel, and a method of manufacturing the same.
2. Discussion of Related Art
As a semiconductor device is highly integrated, efforts for improving performance such as an operating speed and a driving capability have been made. As a MOSFET has also undergone a continuous size reduction, a problem regarding reliability such as a short channel effect is being caused.
In order to solve such problems, a dual-gate structure which forms a gate electrode on both sides of a channel through which an electrical current flows has been introduced. U.S. Pat. No. 6,413,802 (Jul. 2, 2002) discloses a dual-gate structure which has a channel perpendicularly extended from a substrate. The dual-gate structure suppresses a short channel effect since a gate electrode is formed on both sides of a channel and thus current control capability in the channel by a gate voltage is improved.
Recently, a tri-gate structure which extends a concept of the dual-gate structure has been introduced. A conventional tri-gate FinFET is manufactured on a silicon on insulator (“SOI”) substrate that a silicon layer 11, an oxide layer 12 and a silicon layer 13 are stacked as shown in FIGS. 1a and 1b. A silicon pattern 13 of a fin structure formed by patterning the silicon layer 13 defines source and drain regions 13a and 13b and a channel region 13c. The channel region 13c between the source and drain regions 13a and 13b is formed to have a width smaller than those of the source and drain regions 13a and 13b. A gate oxide layer 14 is formed on a surface of the silicon pattern 13 corresponding to the channel region 13c. A gate electrode 15 is formed on the gate oxide layer 14 and the oxide layer 12.
A nano-level FinFET having a single silicon fin 13 has a tri-gate structure such that the gate electrode 15 is formed to cover an upper surface and both side surfaces, i.e., three (3) surfaces of the silicon fin 13.
Thus, a full depletion layer is formed in the silicon fin 13 of the channel region 13c below the gate electrode 15 due to a voltage applied to the gate electrode 15 and the source and drain regions 13a and 13b, and as gate and drain voltages are increased, a drain current is increased through an edge of the silicon fin 13 of the channel region 13c. 
The tri-gate FinFET has an advantage in that a height H and a width W of the silicon fin are diversely changeable compared to the dual-gate FinFET. However, a drain current according to a gate voltage is almost constant since a cross-section area (H*W) of the silicon fin is almost constantly maintained, and the height of the silicon fin is restricted by a channel width that the full depletion is required. Here, a magnitude of the drain current is determined by the width and the height of the silicon fin, and accordingly a specification of the gate and drain voltages and the silicon fin becomes a major parameter which determines a device characteristic. As described above, the conventional tri-gate FinFET has a structural limitation in increasing the drain current. As a result, there is a limitation in obtaining current driving capability per unit area in terms of integration.